Essay about Science

TARCAD: A Template Structure for Reconfigurable Accelerator Styles Muhammad Shafiq, Miquel Peric` s


Nacho Navarro

Eduard Ayguad´


Computer system Sciences

Dept. Arquitectura sobre Computadors

Pc Sciences

Barcelona Supercomputing Centre

Universitat Polit` cnica sobre Catalunya Barcelona Supercomputing Center e

Barcelona, Spain

Barcelona, Spain

Barcelona, Spain

muhammad.shafiq, miquel.pericas @bsc. fue

[email protected] upc. edu

eduard. [email protected] fue

Abstract—In the race towards computational efficiency,

accelerators are achieving prominence. Among the different

types, accelerators built employing reconfigurable fabric, such as FPGAs, have an enormous potential as a result of ability to

personalize the equipment to the application. However , the possible lack of a standard design and style methodology prevents the usage of

such devices besides making difficult the portability and reusability across designs. In addition , generation of highly customized circuits would not integrate properly with high level synthesis equipment. In this job, we present TARCAD, a template structure

to design reconfigurable accelerators. TARCAD enables substantial

customization inside the data administration and figure out engines

although retaining a programming style based on general programming concepts. The template features generality and scalable performance over a variety of FPGAs. We describe the

template buildings in detail and show how to apply five essential scientific kernels: MxM, Audio Wave Equation,

FFT, SpMV and Smith Waterman. TARCAD is in contrast

with other Higher level Synthesis designs and is evaluated

against GPUs, an structures that is much less customizable

and, therefore , also easier to concentrate on from an easy and lightweight programming style. We evaluate the TARCAD template and

compare it is efficiency on a large Xilinx Virtex-6 system to that of several recent GPU research.


The mixing levels of current FPGA devices advanced

until all features of a complex application

kernel can be mapped in a single nick. However , these types of high

denseness FPGAs look just like a sea of reasoning slices and

embedded functionality cores such as general purpose cpus, multipliers/adders, multi-ported SRAMs and DSP pieces etc . Presently, it all depends on the FPGA software designer and just how well he maps a credit card applicatoin to the unit.

This practice is troublesome for several reasons. First, it is just a low-level approach that requires quite a lot of effort

to get mapping the full application. Second, reusability

of modules around projects is usually significantly lowered. And,

finally, it is difficult to scientifically compare hardware implementations that adhere to different high-level agencies and cadre. This emphasizes the need to

subjective out these specific hardware structures in a standard architectural design framework.

Most of the studies which have ported applications to

multiple accelerator architectures (like, for example , Cope

et al [1], Garland et 's. [2] or Shafiq ou al. [3]) identify that two factors will be the most critical kinds to achieve high end for a software. The first factor is a intrinsic

parallelism available in the algorithm being mapped for the

accelerator. The 2nd factor is definitely how efficiently the designer arranges the data to be fed to the computational methods.

FPGA's potentially have to exploit quite a few factors in the best maximized way. Nevertheless , future FPGAs will not

turn into mainstream accelerators if they are unable to solve

the long-standing concern of employing applications in

a well defined, simple and efficient way.

Various application kernels from the HPC domain

have already been ported to reconfigurable devices. However , the majority of

designs are specialized to a single environment due to the

lack of a standard design and style methodology. This work is a

step on the harmonization of data-flow architectures

for different FPGA-based applications written in HDLs (e. g.

Verilog, VHDL) and...

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